TMS320VC5401 datasheet(24/81 Pages) TI

24 / 81 page

Functional Overview

December 2000 − Revised February 2004

SPRS153C

3.2.2 Extended Program Memory

The 5401 uses a paged extended memory scheme in program space to allow access of up to 1024K program

memory locations. In order to implement this scheme, the 5401 includes several features that are also present

on the 548/549 devices:

•

Twenty address lines, instead of sixteen

•

An extra memory-mapped register, the XPC register, defines the page selection. This register is

memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.

•

Six extra instructions for addressing extended program space. These six instructions affect the XPC.

− FB[D] pmad (20 bits) − Far branch

− FBACC[D] Accu[19:0] − Far branch to the location specified by the value in accumulator A or

accumulator B

− FCALL[D] pmad (20 bits) − Far call

− FCALA[D] Accu[19:0] − Far call to the location specified by the value in accumulator A or

accumulator B

− FRET[D] − Far return

− FRETE[D] − Far return with interrupts enabled

•

In addition to these new instructions, two 54x instructions are extended to use 20 bits in the 5401:

− READA data_memory (using 20-bit accumulator address)

− WRITA data_memory (using 20-bit accumulator address)

All other instructions, software interrupts and hardware interrupts do not modify the XPC register and access

only memory within the current page.

Program memory in the 5401 is organized into 16 pages that are each 64K in length, as shown in Figure 3−4.

TMS320VC5401 bảng dữ liệu(PDF) 24 Page - Texas Instruments