TMS320VC5401 datasheet(33/81 Pages) TI

33 / 81 page

Functional Overview

December 2000 − Revised February 2004

SPRS153C

NOTE: All revisions of the 5401 can be operated with an external clock source, provided that the proper voltage levels

be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8 V power supply

(CVDD), rather than the 3 V I/O supply (DVDD). Refer to the recommended operating conditions section of this document

for the allowable voltage levels of the X2/CLKIN pin.

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides

various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can

be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a

built-in software-programmable PLL can be configured in one of two clock modes:

•

PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved

using the PLL circuitry.

•

DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can

be completely disabled in order to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode

reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the

CLKMD1 − CLKMD3 pins as shown in Table 3−7.

Table 3−7. Clock Mode Settings at Reset

CLKMD1

CLKMD2

CLKMD3

CLKMD

RESET VALUE

CLOCK MODE

CLKMD1

CLKMD2

CLKMD3

RESET VALUE

CLOCK MODE

E007h

PLL x 15

9007h

PLL x 10

4007h

PLL x 5

1007h

PLL x 2

F007h

PLL x 1

0000h

1/2 (PLL disabled)

F000h

1/4 (PLL disabled)

—

Reserved (bypass mode)

3.8

DMA Controller

The 5401 direct memory access (DMA) controller transfers data between points in the memory map without

intervention by the CPU. The DMA controller allows movements of data to and from internal program/data

memory or internal peripherals (such as the McBSPs) to occur in the background of CPU operation. The DMA

has six independent programmable channels allowing six different contexts for DMA operation.

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