TMS320VC5401 datasheet(34/81 Pages) TI

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Functional Overview

December 2000 − Revised February 2004

SPRS153C

3.8.1 Features

The DMA has the following features:

•

The DMA operates independently of the CPU.

•

The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.

•

The DMA has higher priority than the CPU for internal accesses.

•

Each channel has independently programmable priorities.

•

Each channels source and destination address registers can have configurable indexes through memory

on each read and write transfer, respectively. The address may remain constant, be post-incremented,

post-decremented, or be adjusted by a programmable value.

•

Each read or write transfer may be initialized by selected events.

•

Upon completion of a half-block or an entire-block transfer, each DMA channel may send an interrupt to

the CPU.

•

The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words).

3.8.2 DMA Memory Map

The DMA memory map is shown in Figure 3−10 to allow DMA transfers to be unaffected by the status of the

MPMC, DROM, and OVLY bits.

FFFF

Reserved

3000

2FFF

Hex

0000

005F

0060

Scratch-Pad

0080

007F

RAM†

Reserved

McBSP

Registers

001F

0020

0023

0024

1000

0FFF

Reserved

On-Chip DARAM

(4K x 16-bit)

1FFF

2000

On-Chip DARAM

(4K x 16-bit)

Reserved

† The scratch-pad RAM area is physically a part of the DARAM block starting at address 1000h. Physical location can

affect multiple access performance. (See Section 3.1.2.)

Figure 3−10. DMA Memory Map

3.8.3 DMA Priority Level

Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple

DMA channels that are assigned to the same priority level are handled in a round-robin manner.

3.8.4 DMA Source/Destination Address Modification

The DMA provides flexible address-indexing modes for easy implementation of data management schemes

such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and

can be post-incremented, post-decremented, or post-incremented with a specified index offset.

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