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VT82C596 bảng dữ liệu(PDF) 90 Page - List of Unclassifed Manufacturers

tên linh kiện VT82C596
Giải thích chi tiết về linh kiện  PCI INTEGRATED PERIPHERAL CONTROLLER
PDF  96 Pages
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nhà sản xuất  ETC [List of Unclassifed Manufacturers]
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VT82C596 bảng dữ liệu(HTML) 90 Page - List of Unclassifed Manufacturers

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VT82C596B
Revision 0.3 June 17, 1999
-84-
Electrical Specifications
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Table 7. AC Characteristics - UltraDMA-33 IDE Bus Interface Timing
Symbol
Description
Timing
Unit
TENV1
Envelope time for read initial
29.3
ns
TDS1
Data setup time for read initial
1.1
ns
TDH1
Data hold time for read initial (rise)
2.3
ns
TENV2
Envelope time for write initial (rise)
29.3
ns
TDVS2
Data setup time for write initial (fall)
42.2
ns
TDVH2
Data hold time for write initial (fall)
17.8
ns
TDVS2
Data setup time for write initial
42.0
ns
TDVH2
Data hold time for write initial
17.2
ns
TRFS
READY to final STROBE time
21.3
ns
TRP
READY to Pause time
180.0
ns
TLI4
Limited interlock time (to STOP)
95.1
ns
TLI4
Limited interlock time (to Host DMARDY)
125.3
ns
TZA4
Delay time required for output drives turning on
102.0
ns
TDVS4
Data setup time for read terminating
55.3
ns
TDVH4
Data hold time for read terminating
31.6
ns
TLI5
Limited interlock time (to STOP)
125.3
ns
TLI5
Limited interlock time (to Host STROBE)
95.2
ns
TMIL5
Limited interlock time with minimum
120.6
ns
TDVS5
Data setup time for write terminating
57.7
ns
TDVH5
Data hold time for write terminating
31.8
ns
TMIL6
Limited interlock time with minimum
155.8
ns
TZA6
Delay time required for output drives turning on
68.5
ns
TLI5
Limited interlock time
65.2
ns
TMIL5
Limited interlock time with minimum
90.6
ns
T2
Delay time of PCLK to DCS3,1#
4.8
ns
T3
Delay time of PCLK to DA[2:0]
5.3
ns
T4
Delay time of PCLK to DIOW#
9.3
ns
T5
Delay time of PCLK to DIOR#
9.2
ns
TWDS
Data setup time during PIO write
85.5
ns
TWDH
Data hold time during PIO write
31.7
ns
TRDS
Data setup time during PIO read
0.4
ns
TRDH
Data hold time during PIO read
2.1
ns



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