VT82C596 datasheet(65/96 Pages) ETC

65 / 96 page

VT82C596B

Revision 0.3 June 17, 1999

-59-

Function 3 Registers - Power Management and SMBus

7HFKQRORJLHV ,QF

:H &RQQHFW

Power Management-Specific PCI Configuration Registers

Offset 40 - Debounce Control...........................................RW

7-6

Reserved

........................................ always reads 0

Debounce LID and PWRBTN# Inputs for 200us

Disable ...................................................default

1Enable

4-0

Reserved

........................................ always reads 0

Offset 41 - General Configuration (00h)......................... RW

I/O Enable for ACPI I/O Base

Disable access to ACPI I/O block.......... default

Allow access to Power Management I/O

base address for this register block).

The

definitions of the registers in the Power

Management I/O Register Block are included

later in this document, following the Power

Management Subsystem overview.

ACPI Timer Reset

Disable................................................... default

1Enable

5-4

Reserved (Do Not Program) ...................... default = 0

ACPI Timer Count Select

24-bit Timer........................................... default

32-bit Timer

RTC Enable Signal Gated with PSON (SUSC#) in

Soft-Off Mode

Disable................................................... default

1Enable

Clock Throttling Clock Selection

32 usec (512 usec cycle time) ................ default

1 msec (16 msec cycle time)

Reserved (Do Not Program) ...................... default = 0

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