CP3SP33SMSSLASHNOPB datasheet(156/407 Pages) TI1

156 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

SENTSTALL

The Sent STALL Handshake bit is set when a STALL handshake is

transmitted. Software clears this bit to detect the next STALL handshake.

0 – No STALL handshake since the bit was last cleared.

1 – STALL handshake transmitted.

DATAEND

The Data End bit is set by software under three circumstances: when setting

the TXPKTRDY bit for the last data packet, when clearing the RXPKTRDY bit

after unloading the last data packet, or when setting the TXPKTRDY bit for a

zero-length data packet. The bit is cleared automatically.

0 – Not the end of the data.

1 – Last or zero-length data packet.

SETUPEND

The Setup End bit is set when a control transaction ends before the DATAEND

bit has been set. An interrupt will be asserted and the FIFO flushed at this time.

The bit is cleared by writing a 1 to the SERVICEDSETUPEND bit.

0 – No unexpected end of control transaction.

1 – Unexpected end of control transaction.

SENDSTALL

The Send STALL Handshake bit is written with 1 to terminate the current

transaction. The STALL handshake will be transmitted, and then this bit will be

cleared automatically.

0 – Normal operation.

1 – Write 1 to send the STALL handshake.

SERVICEDRXPKTRDY The Serviced Receive Packet Ready bit is written with 1 to clear the

RXPKTRDY bit. The SERVICEDRXPKTRDY bit is cleared automatically.

0 – Normal state.

1 – Write 1 to clear the RXPKTRDY bit.

SERVICEDSETUPEND The Serviced Setup End bit is written with 1 to clear the SETUPEND bit. The

SERVICEDSETUPEND bit is cleared automatically.

0 – Normal state.

1 – Write 1 to clear the SETUPEND bit.

FLUSHFIFO

The Flush FIFO bit is written with 1 to flush the Endpoint 0 FIFO. The FIFO

pointer is reset and the TXPKTRDY/RXPKTRDY bit is cleared. The

FLUSHFIFO bit has no effect unless TXPKTRDY/RXPKTRDY bit is set. The

FLUSHFIFO bit is cleared automatically.

0 – Normal operation.

1 – Flush the Endpoint 0 FIFO and clear the TXPKTRDY/RXPKTRDY bit.

Host Mode Format

NAKTIME

STATUS

SETUP

Reserved

FLUSHFIFO

REQPKT

ERROR

RXSTALL

TXPKTRDY

RXPKTRDY

OUT

PKT

RXPKTRDY

The Receive Packet Ready bit is set when a data packet has been received. An

interrupt is asserted (if enabled) when this bit is set. Software clears this bit after

unloading the packet from the FIFO to detect the next packet.

0 – No data packet received.

1 – Data packet received.

TXPKTRDY

The Transmit Packet Ready bit is set by software after loading a data packet into the

FIFO. The bit is cleared automatically when the data packet has been transmitted. An

interrupt is asserted (if enabled) when this bit is cleared.

0 – No packet in transmit FIFO.

1 – Data packet in FIFO, ready to transmit.

156

USB Controller

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB bảng dữ liệu(PDF) 156 Page - Texas Instruments

CP3SP33SMS/NOPB bảng dữ liệu(HTML) 156 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL