CP3SP33SMSSLASHNOPB datasheet(142/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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COMPC0

20.10.12 Codec Compensation Filter C1/3 Tap Register (TCDCCOMP1)

The TCDCCOMP1 register is a 16-bit, read/write register that specifies the C1 and C3 coefficients of the

compensation filter, when the CUSTCOMP bit of the TCDCDSP register is set. When the CUSTCOMP bit

is clear, the TCDCCOMP1 register is ignored. After reset, this register is cleared to 0000h

COMPC1

20.10.13 Codec Compensation Filter C2 Tap Register (TCDCCOMP2)

The TCDCCOMP2 register is a 16-bit, read/write register that specifies the C2 coefficient of the

compensation filter, when the CUSTCOMP bit of the TCDCDSP register is set. When the CUSTCOMP bit

is clear, the TCDCCOMP2 register is ignored. After reset, this register is cleared to 0000h

COMPC2

20.10.14 Codec ADC Data Register n (TCDCADCn)

The TCDCADCn registers are 16-bit, read-only registers used to unload a word from the corresponding

ADC FIFOs. After reset, these registers are cleared to 0000h

ADCDATA

20.10.15 Codec Left Channel DAC Data Register (TCDCLEFT)

The TCDCLEFT register is a 16-bit, read/write register used to load a word into the left-channel DAC

FIFO. After reset, this register is cleared to 0000h

LEFTDATA

20.10.16 Codec Right Channel DAC Data Register (TCDCRIGHT)

The TCDCRIGHT register is a 16-bit, read/write register used to load a word into the right-channel DAC

FIFO. After reset, this register is cleared to 0000h

RIGHTDATA

20.10.17 Codec Debug Register (TCDCDEBUG)

The TCDCDEBUG register is a 16-bit, read/write register used to configure the TCIO1 pin and safely reset

the codec. After reset, this register is cleared to 0000h.

4 3

Reserved

SFTRST

Reserved

GPIO

The GPIO field configures the TCIO1 pin (alternate function of PG10).

142

Telematics Codec

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