DP83907 datasheet(41/70 Pages) NSC

41 / 70 page

60 Operation of DP83907 (Continued)

TLF12082 – 22

FIGURE 27 DP83907 Bus Architecture

62 BUFFER MEMORY ACCESS CONTROL (DMA)

The buffer memory control capabilities of the DP83907

greatly simplify the use of the DP83907 in typical configura-

tions The local DMA channel transfers data between the

FIFO and memory On transmission the packet is DMA’d

from memory to the FIFO in bursts Should a collision occur

(up to 15 times) the packet is re-transmitted with no proces-

sor intervention On reception packets are moved via DMA

from the FIFO to the receive buffer ring (as explained be-

low)

A Remote DMA channel is also provided on the DP83907 to

accomplish transfers between a buffer memory and an in-

ternal Data Port when using the DP83907 in IO Mode This

Remote DMA channel is not used when the DP83907 is

used in a shared Memory mode In this second mode the

buffer memory is dual ported and directly mapped into the

system memory In this mode the system CPU directly ac-

cesses the RAM under software control to transfer packet

data

The following sections describe the operation of the Local

DMA channel for packet reception which is used in both

modes For Shared Memory mode the description of the

Remote DMA does not apply

For reference an example configuration using the DP83907

is shown in

Figure 27

TLF12082 – 23

FIGURE 28 DP83907 Receive Buffer Ring

DP83907 bảng dữ liệu(PDF) 41 Page - National Semiconductor (TI)