PXA270 datasheet(49/126 Pages) INTEL

49 / 126 page

Electrical, Mechanical, and Thermal Specification

4-29

Intel® PXA270 Processor

Pin Listing and Signal Definitions

The address signals are driven low and data signals are pulled low during sleep, standby, deep-

sleep, frequency-change modes, and manual self-refresh. All other memory control signals are in

the same state that they are in after a hardware reset. If the SDRAMs are in self-refresh mode, they

are kept there by driving SDCKE low.

4.5

Power-Supply Pins

Table 4-5 summarize the power-supply ball count.

§§

nPOE

GPIO (memory controller drives high)

nPWE

GPIO (memory controller drives high)

NOTE:

† This indicates that the GPIO pin, if configured for the alternate function

used by the memory controller during reset, drives the represented

value.

NOTE: SCLK<3> is only available on PXA270 processor family packages

1. MA pins are driven

2. MD pins are pulled low

Table 4-4. Memory Controller Pin Reset Values (Sheet 2 of 2)

Pin Name

Reset, Sleep, Standby, Deep-Sleep, Frequency

Change, and Manual Self-Refresh Mode Values

Table 4-5. Discrete (13x13 VF-BGA) Power Supply Pin Summary

Name

Number of Package Balls

13x13 mm VF-BGA

Number of Pachage Balls

23x23 mm PBGA

VCC_BATT

VCC_IO

VCC_USB

VCC_LCD

VCC_MEM

VCC_BB

VCC_PLL

VCC_SRAM

VCC_CORE

VCC_USIM

VSS

VSS_IO

VSS_MEM

VSS_BB

VSS_PLL

VSS_CORE

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