ADSP-SC583 datasheet(99/168 Pages) AD

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Giải thích chi tiết về linh kiện	SHARC plus Dual Core DSP with ARM Cortex-A5

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Preliminary Technical Data

Rev. PrF

Page 99 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

Mobile DDR SDRAM Read Cycle Timing

Table 51 and Figure 21 show mobile DDR SDRAM read cycle timing, related to the dynamic memory controller (DMC).

Table 51. Mobile DDR SDRAM Read Cycle Timing, VDD_DMCx Nominal 1.8 V

1 Specifications apply to both DMC0 and DMC1.

All specifications are based on simulation data and are subject to change without notice.

200 MHz2

2 In order to ensure proper operation of LPDDR, all the LPDDR guidelines must be strictly followed (see Engineer-to-Engineer Note EE-TBD).

Parameter

Min

Max

Unit

Timing Requirements

tQH

DMCx_DQ, DMCx_DQS Output Hold Time From DMCx_DQS

1.75

tDQSQ

DMCx_DQS-DMCx_DQ Skew for DMCx_DQS and Associated

DMCx_DQ Signals

0.4

tRPRE

Read Preamble

0.9

1.1

tCK

tRPST

Read Postamble

0.4

0.6

tCK

Figure 21. Mobile DDR SDRAM Controller Input AC Timing

DMCx_CK

DMCx_LDQS/DMCx_HDQS

tDQSQ

DMCx_DQx

(DATA)

Dn+1

Dn+2

Dn+3

tRPRE

tRPST

tQH

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