ADSP-SC583 datasheet(90/168 Pages) AD

90 / 168 page

Rev. PrF

Page 90 of 168

February 2016

Preliminary Technical Data

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

Asynchronous Read

Table 41 and Figure 12 show asynchronous memory read timing, related to the static memory controller (SMC).

Table 41. Asynchronous Memory Read

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tSDATARE

DATA in Setup Before SMC0_ARE High

5.1

tHDATARE

DATA in Hold After SMC0_ARE High

0.7

tDARDYARE

SMC0_ARDY Valid After SMC0_ARE Low1, 2

1 SMC0_BxCTL.ARDYEN bit = 1.

2 RAT value set using the SMC_BxTIM.RAT bits.

(RAT – 2.5) × tSCLK0 – 17.5

Switching Characteristics

tAMSARE

ADDR/SMC0_AMSx Assertion Before SMC0_ARE

Low3

3 PREST, RST, and PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, and the SMC_BxETIM.PREAT bits.

(PREST + RST + PREAT) × tSCLK0 – 2

tAOEARE

SMC0_AOE Assertion Before SMC0_ARE Low

(RST + PREAT) × tSCLK0 – 2

tHARE

Output4 Hold After SMC0_ARE High5

4 Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE, SMC0_ABEx.

5 RHT value set using the SMC_BxTIM.RHT bits.

RHT × tSCLK0 –2

tWARE

SMC0_ARE Active Low Width6

6 SMC0_BxCTL.ARDYEN bit = 0.

RAT × tSCLK0 – 2

tDAREARDY

SMC0_ARE High Delay After SMC0_ARDY

Assertion1

2.5 × tSCLK0

3.5 × tSCLK0 + 17.5

Figure 12. Asynchronous Read

SMC0_ARE

SMC0_AMSx

SMC0_Ax

tWARE

SMC0_AOE

SMC0_Dx (DATA)

SMC0_ARDY

tAOEARE

tAMSARE

tDARDYARE

tHARE

tHDATARE

tDAREARDY

tSDATARE

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