ADSP-SC583 datasheet(6/168 Pages) AD

6 / 168 page

Rev. PrF

Page 6 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587 Preliminary Technical Data

Generic Interrupt Controller, PL390 (ADSP-SC58x only)

The generic interrupt controller (GIC) is a centralized resource

for supporting and managing interrupts. The ADSP-SC58x pro-

cessor has a uniprocessor implementation of the GIC. The GIC

splits logically into GICPORT0 (distributor block) and

GICPORT1 (CPU interface block).

Generic Interrupt Controller Port0 (GICPORT0)

The GICPORT0 (distributor) performs interrupt prioritization

and distribution to the GICPORT1 (CPU interface) blocks that

connect to the processors in the system. It centralizes all inter-

rupt sources, determines the priority of each interrupt, and

forwards the interrupt with the highest priority to the interface,

for priority masking and preemption handling.

Generic Interrupt Controller Port1 (GICPORT1)

GICPORT1 (CPU interface) block performs priority masking

and preemption handling for a connected processor in the sys-

tem. GICPORT1 supports 8 SGIs (software generated

interrupts) and 254 SPIs (shared peripheral interrupts).

L2 Cache Controller, PL310 (ADSP-SC58x only)

The L2 cache controller PL310 (Figure 2) works efficiently with

ARM processors that implement system fabric. The cache con-

troller directly interfaces on the data and instruction interface.

The internal pipelining of the cache controller is optimized to

enable the processors to operate at the same clock frequency.

The cache controller supports:

• Two read/write 64-bit slave ports for interfacing with data

and instruction interfaces or for data between ARM and

SHARC cores

• Two read/write 64-bit master ports for interfacing with the

system fabric

SHARC PROCESSOR

As shown in Figure 3, the SHARC processor integrates a

SHARC+ SIMD core, L1 memory crossbar, I/D cache control-

ler, L1 memory blocks, and the master/slave ports. The

SHARC+ SIMD core is shown in Figure 4.

The SHARC processor supports a modified Harvard architec-

ture in combination with a hierarchical memory structure.

Level 1 (L1) memories typically operate at the full processor

speed with little or no latency.

Figure 3. SHARC Processor Block Diagram

RAM

I-CACHE

RAM

P-CACHE

RAM

P-CACHE

RAM

D-CACHE

RAM

P-CACHE

RAM

P-CACHE

RAM

D-CACHE

RAM

P-CACHE

RAM

P-CACHE

RAM

IO (32)

INTERNAL MEMORY INTERFACE (IMIF)

I/D CACHE CONTROL

SHARC+

SIMD CORE

SLAVE

PORT 1

SLAVE

PORT 2

IO (32)

CORE

MMR

DM (64)

PM (64)

PS (64/48)

(32)

MASTER

PORT INSTRUCTION

MASTER

PORT DATA

IO (32)

CMD (64)

CMI (64)

SYSTEM FABRIC

SYSCLK

DOMAIN

INTERRUPT

SEC

SIMD Processor

CCLK DOMAIN

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