ADSP-SC583 datasheet(91/168 Pages) AD

91 / 168 page

Preliminary Technical Data

Rev. PrF

Page 91 of 168

February 2016

ADSP-SC582/583/584/587/589/ADSP-21583/584/587

Asynchronous Flash Read

Table 42 and Figure 13 show asynchronous flash memory read timing, related to the static memory controller (SMC).

Table 42. Asynchronous Flash Read

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Switching Characteristics

tAMSADV

SMC0_Ax (Address)/SMC0_AMSx Assertion Before SMC0_NORDV

Low1

1 PREST value set using the SMC_BxETIM.PREST bits.

PREST × tSCLK0 – 2

tWADV

SMC0_NORDV Active Low Width2

2 RST value set using the SMC_BxTIM.RST bits.

RST × tSCLK0 – 2

tDADVARE

SMC0_ARE Low Delay From SMC0_NORDV High3

3 PREAT value set using the SMC_BxETIM.PREAT bits.

PREAT × tSCLK0 – 2

tHARE

Output4 Hold After SMC0_ARE High5

4 Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE.

5 RHT value set using the SMC_BxTIM.RHT bits.

RHT × tSCLK0 – 2

tWARE

6 SMC0_BxCTL.ARDYEN bit = 0.

SMC0_ARE Active Low Width7

7 RAT value set using the SMC_BxTIM.RAT bits.

RAT × tSCLK0 – 2

Figure 13. Asynchronous Flash Read

SMC0_Ax

(NOR_Ax)

tAMSADV

tDADVARE

tWADV

tWARE

tHARE

READ LATCHED

DATA

SMC0_AMSx

(NOR_CE)

SMC0_ARE

(NOR_OE)

SMC0_Dx

(NOR_Dx)

SMC0_AOE

(NOR_ADV)

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