UT700 datasheet(25/46 Pages) AEROFLEX

tên linh kiện	UT700

Giải thích chi tiết về linh kiện	UT700 32-bit Fault-Tolerant SPARCTM V8/LEON 3FT Processor

PDF	46 Pages

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25 / 46 page

36-00-00-000

Ver. 1.3.1

Aeroflex Microelectronics Solutions - HiRel

4.0 Timing Specifications

4.1 Power Sequencing and Reset

(VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55

oC to 105oC)

Notes:

1. Guaranteed by design.

Symbol

Description

Conditions

Min

Max

Units

tVCD

VDD valid to VDDC delay

VDD > 3.0V; VDDC > 1.1V

tVHBZ

VDD valid to control signals high-z

(WRITE, OE, IOS, ROMS[1:0], RWE[3:0],

RAMOE [4:0], READ SDWE, and

SDCS[1:0])

VDD valid to outputs high-z

([DATA[31:0], CB[15:0], and GPIO[15:0])

VDD > 1.5V; VDDC = 0V

tCLK

tCHBV

VDDC valid to control signals valid-inactive

(WRITE, OE, IOS, ROMS[1:0], RWE[3:0],

RAMOE [4:0], READ SDWE, and

SDCS[1:0])

VDD > 3.0V; VDDC > 1.1V

tCLK

tRESET1

VDDC valid to RESET deassert

VDDC > 1.1V

tCLK

tRESET2

RESET deasserted to outputs valid-active

(ROMS[0] and OE)

tCLK

tRESET3

RESET asserted to control signals valid-

inactive

(WRITE, OE, IOS, ROMS[1:0], RWE[3:0],

RAMOE [4:0], READ SDWE, and

SDCS[1:0])

RESET asserted to outputs high-z

(DATA[31:0], CB[15:0], and GPIO[15:0])

tCLK

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