UT700 datasheet(26/46 Pages) AEROFLEX

26 / 46 page

36-00-00-000

Ver. 1.3.1

Aeroflex Microelectronics Solutions - HiRel

Figure 4. Power Sequencing and Reset Timing Diagram

4.1.1. Power Sequencing

For optimal power sequencing, both power-up and power-down, ramp both VDD and VDDC together. During power-up, if VDDC >

VDD + 0.3V, excessive current or damage may occur to the device. During power down, it is acceptable for VDD to be less than

VDDC by more than 0.3V as long as VDDC is not actively driven.

4.1.2 Bus Control and Bi-Direct Fail-Safe Circuitry

In order to prevent bus contention on the external memory interface while VDDC is ramping up, the UT700 has functionality to

ensure that the bi-direct and memory bus control signals described in Section 4.1 will be in a high-z state tVHBZ delay after VDD

reaches 1.5V. The core logic will put these signals into their valid-inactive states tCHBV clock cycles after VDDC reaches 1.1V.

Aeroflex recommends that users place pull-up resistors on the indicated output enable, write enable, and chip select pins, and a pull-

down resistor on the READ pin, if tVCD is greater than 100ns. This will prevent bus capacitance or transients from inadvertently

placing these pins in an active state, which could result in external memory devices driving the address and data buses.

4.1.3 Reset Circuitry

The reset circuitry is controlled by the core logic; therefore, the circuitry is functional only after VDDC reaches its minimum operat-

ing voltage of 1.1V. After VDDC is stable, the system must continue to assert RESET for a minimum of tRESET1 clock cycles before

it can be de-asserted. Asserting RESET for less time could result in the RESET signal not being recognized.

The UT700 will begin fetching code from external memory no more than tRESET2 clock cycles after RESET is de-asserted. Control

signals ROMS[0] and OE will be driven to their valid-active states in order for the UT700 to begin fetching code from PROM.

During normal operation, the indicated bus control signals will go to a valid-inactive state, and the bi-directs will go to a high-z

state, within tRESET3 clock cycles after the assertion of RESET.

VALID-INACTIVE

VALID-ACTIVE

VALID-INACTIVE

VALID-ACTIVE

tRESET3

tVHBZ

tRESET3

tRESET2

tCHBV

tVHBZ

tRESET1

tVCD

SYSCLK

VDD 3.3V

VDDC 1.2V

RESET

Memory Bus

Tri-State Outputs

Control Signals

UT700 bảng dữ liệu(PDF) 26 Page - Aeroflex Circuit Technology

UT700 bảng dữ liệu(HTML) 26 Page - Aeroflex Circuit Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

bảng dữ liệu tải về

Link URL