16

36-00-00-000

Ver. 1.3.1

Aeroflex Microelectronics Solutions - HiRel

2.20 Bootstrap Signals

The states of the following signals are latched in upon the rising edge of reset in order to configure the UT700 for the indicated

operation.

N/C

D4, D18, E4, J18, L4, V9

No connect. These pins may be left

Unused

D8

This pin may be left floating or tied to

Unused

D19

Pin Name

Function

GPIO[1:0]

Sets the data width of the PROM area

00: 8 bits

01: 16 bits

10: 32 bits

11: Not used

GPIO[2]

Enable EDAC checking of the PROM area

0: EDAC disabled

1: EDAC enabled

GPIO[7:4]

Set the SpW clock divisor link bits in the SpW Clock Divisor Register

GPIO[15:12]

Sets the least significant address nibble of the IP and MAC address for the Ethernet Debug Commu-

nication Link (EDCL)

Pin Name

Pin Number

Description

484 CLGA