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RF430CL330HCPWR bảng dữ liệu(PDF) 32 Page - Texas Instruments |
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RF430CL330HCPWR bảng dữ liệu(HTML) 32 Page - Texas Instruments |
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32 / 47 page  RF430CL330H SLAS916C – NOVEMBER 2012 – REVISED NOVEMBER 2014 www.ti.com 5.8.3 Data Rate Settings 106-kbps, 212-kbps, 424-kbps, and 848-kbps data rates are supported by the device. The device always answers ATTRIB commands from the PCD that request higher data rates. Note, this is not NFC-compliant, because for NFC-B the maximum data rate specified is 106 kbps. It is assumed that an NFC-compliant PCD would not request higher data rates thus no interoperability issues are expected. Even though all data rates up to 848 kbps are supported, the device by default reports only the capability to support 106 kbps to the PCD. To change this behavior, follow these steps using the selected serial interface (I2C or SPI): 1. Read the version register. 2. Use the version register content to select one of the following sequences: – If "Software Identification" = 01h and "Software Version" = 01h, follow the sequence in Table 5-28. – If "Software Identification" = 01h and "Software Version" = 02h , follow the sequence in Table 5-29. 3. If you do not want to support all data rates up to 847 kbps, then change the Data Rate Capability byte (Data 0 of Step 3. Write Access) according to Table 5-30. 4. Perform the steps in the following tables. Table 5-28. Data Rate Setting Sequence (Version = 0101h) Addr Bits Addr Bits Access Type Data 0 Data 1 15 to 8 7 to 0 1. Write Access 0xFF 0xE0 0x4E 0x00 2. Write Access 0xFF 0xFE 0x80 0x00 3. Write Access 0x2A 0xA4 0xC4(1) 0x00 4. Write Access 0x28 0x14 0x00 0x00 5. Write Access 0xFF 0xE0 0x00 0x00 (1) Data Rate Capability according to Table 5-30. 0xC4: all data rates up to 847 kbps are supported. Table 5-29. Data Rate Setting Sequence (Version = 0201h) Addr Bits Addr Bits Access Type Data 0 Data 1 15 to 8 7 to 0 1. Write Access 0xFF 0xE0 0x4E 0x00 2. Write Access 0xFF 0xFE 0x80 0x00 3. Write Access 0x2A 0x7C 0xC4(1) 0x00 4. Write Access 0x28 0x14 0x00 0x00 5. Write Access 0xFF 0xE0 0x00 0x00 (1) Data Rate Capability according to Table 5-30. 0xC4: all data rates up to 847 kbps are supported. Table 5-30. Data Rate Capability Data Rata Capability Byte Description b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 PICC supports only 106-kbps in both directions (default). 1 x x x 0 x x x Same data rate from PCD to PICC and from PICC to PCD compulsory x x x 1 0 x x x PICC to PCD, data rate supported is 212 kbps x x 1 x 0 x x x PICC to PCD, data rate supported is 424 kbps x 1 x x 0 x x x PICC to PCD, data rate supported is 847 kbps x x x x 0 x x 1 PCD to PICC, data rate supported is 212 kbps x x x x 0 x 1 x PCD to PICC, data rate supported is 424 kbps x x x x 0 1 x x PCD to PICC, data rate supported is 847 kbps 32 Detailed Description Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: RF430CL330H |
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