DP83867CS datasheet(14/114 Pages) TI1

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GTX

(at Transmitter)

TXD [8:5][3:0]

TXD [7:4][3:0]

TX_CTL

TskewT

TskewR

GTX

(at Receiver)

TXD [3:0]

TXD [8:5]

TXD [7:4]

TXD [4]

TXEN

TXD [9]

TXERR

DP83867CS, DP83867IS, DP83867E

SNLS504 – OCTOBER 2015

www.ti.com

8.10 RGMII Timing

(1)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

TskewT

Data to Clock output Skew

See (2)

-500

500

(at Transmitter)

TskewR

Data to Clock input Skew

See (2)

1.8

2.6

(at Receiver)

TsetupT

Data to Clock output Setup

See (3)

1.2

(at Transmitter – internal

delay)

TholdT

Clock to Data output Hold

See (3)

1.2

(at Transmitter – internal

delay)

TsetupR

Data to Clock input Setup

See (3)

(at Reciever – internal delay)

TholdR

Data to Clock input Setup

See (3)

(at Receiver – internal delay)

Tcyc

Clock Cycle Duration(4)

See (4)

7.2

8.8

Duty_G

Duty Cycle for Gigabit(5)

See (5)

Duty_T

Duty Cycle for 10/100T(5)

See (5)

Rise Time (20% to 80%)

0.75

Fall Time (20% to 80%)

0.75

TTXLAT

RGMII to MDI Latency

See (6)

TRXLAT

MDI to RGMII Latency

See (6)

288

(1)

Ensured by production test, characterization, or design.

(2)

When operating without RGMII internal delay, the PC board design requires clocks to be routed such that an additional trace delay of

greater than 1.5ns is added to the associated clock signal.

(3)

Device may operate with or without internal delay.

(4)

For 10Mbps and 100Mbps, Tcyc will scale to 400ns +/- 40ns and 40ns +/- 4ns.

(5)

Duty cycle may be stretched or shrunk during speed changes or while transitioning to a received packet’s clock domain as long as

minimum duty cycle is not violated and stretching occurs for no more that three Tcyc of the lowest speed transitioned between.

(6)

Operating in 1000Base-T .

Figure 5. RGMII Transmit Multiplexing and Timing Diagram

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