RPC56EL60L5BFSR datasheet(31/137 Pages) STMICROELECTRONICS

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RPC56EL60L5

Introduction

136

exceptions, etc.), allowing the development tool to interpolate what transpires

between the discontinuities. Thus, static code may be traced.

–

Watchpoint messaging (WPM) via the auxiliary port

–

Watchpoint trigger enable of program and/or data trace messaging

–

Data tracing of instruction fetches via private opcodes

1.5.39

IEEE 1149.1 JTAG Controller (JTAGC)

The JTAGC block provides the means to test chip functionality and connectivity while

remaining transparent to system logic when not in test mode. All data input to and output

from the JTAGC block is communicated in serial format. The JTAGC block is compliant with

the IEEE standard.

The JTAG controller provides the following features:



IEEE Test Access Port (TAP) interface with 5 pins:

–TDI

–TMS

–TCK

–TDO

–JCOMP



Selectable modes of operation include JTAGC/debug or normal system operation



5-bit instruction register that supports the following IEEE 1149.1-2001 defined

instructions:

–BYPASS

–

IDCODE

–EXTEST

–SAMPLE

–

SAMPLE/PRELOAD



3 test data registers: a bypass register, a boundary scan register, and a device

identification register. The size of the boundary scan register is parameterized to

support a variety of boundary scan chain lengths.



TAP controller state machine that controls the operation of the data registers,

instruction register and associated circuitry

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