RPC56EL60L5BFSR datasheet(25/137 Pages) STMICROELECTRONICS

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RPC56EL60L5

Introduction

136

1.5.28

Serial communication interface module (LINFlexD)

The LINFlexD module (LINFlex with DMA support) on this device features the following:



Supports LIN Master mode, LIN Slave mode and UART mode



LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications



Manages LIN frame transmission and reception without CPU intervention



LIN features

–

Autonomous LIN frame handling

–

Message buffer to store as many as 8 data bytes

–

Supports messages as long as 64 bytes

–

Detection and flagging of LIN errors (Sync field, delimiter, ID parity, bit framing,

checksum and Time-out errors)

–

Classic or extended checksum calculation

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Configurable break duration of up to 50-bit times

–

Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)

–

Diagnostic features (Loop back, LIN bus stuck dominant detection)

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Interrupt driven operation with 16 interrupt sources



LIN slave mode features

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Autonomous LIN header handling

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Autonomous LIN response handling



UART mode

–

Full-duplex operation

–

Standard non return-to-zero (NRZ) mark/space format

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Data buffers with 4-byte receive, 4-byte transmit

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Configurable word length (8-bit, 9-bit, 16-bit, or 17-bit words)

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Configurable parity scheme: none, odd, even, always 0

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Speed as fast as 2 Mbit/s

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Error detection and flagging (Parity, Noise and Framing errors)

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Interrupt driven operation with four interrupt sources

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Separate transmitter and receiver CPU interrupt sources

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16-bit programmable baud-rate modulus counter and 16-bit fractional

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Two receiver wake-up methods



Support for DMA enabled transfers

1.5.29

Deserial Serial Peripheral Interface (DSPI)

The DSPI modules provide a synchronous serial interface for communication between the

RPC56EL60L5 and external devices.

A DSPI module provides these features:



Full duplex, synchronous transfers



Master or slave operation



Programmable master bit rates



Programmable clock polarity and phase

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