RPC56EL60L5BFSR datasheet(115/137 Pages) STMICROELECTRONICS

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RPC56EL60L5

Electrical characteristics

136

The reset sequences shown in Figure 15 and Figure 16 are triggered by functional reset

events. RESET is driven low during these two reset sequences only if the corresponding

functional reset source (which triggered the reset sequence) was enabled to drive RESET

low for the duration of the internal reset sequence(c).

3.19.3

Reset sequence trigger mapping

The following table shows the possible trigger events for the different reset sequences. It

specifies the reset sequence start conditions as well as the reset sequence end indications

that are the basis for the timing data provided in Table 30.

See RGM_FBRE register for more details.

Table 31. Reset sequence trigger — reset sequence

Reset

Sequence

Trigger

Reset

Sequence

Start

Condition

Reset

Sequence

End

Indication

Reset Sequence

Destructive

Reset

Sequence,

BIST

enabled(1)

Destructive

Reset

Sequence,

BIST

disabled(1)

External

Reset

Sequence

Long, BIST

enabled

Functional

Reset

Sequence

Long

Functional

Reset

Sequence

Short

All internal

destructive reset

sources

(LVDs or internal

HVD during

power-up and

during operation)

Destructive

reset

Release of

RESET(2)

triggers

cannot

trigger

cannot

trigger

cannot

trigger

Assertion of

RESET(3)

External

reset via

RESET

cannot trigger

triggers(4)

triggers(5)

triggers(6)

All internal

functional reset

sources

configured for

long reset

Sequence

starts with

internal reset

trigger

Release of

RESET(7)

cannot trigger

cannot

trigger

triggers

cannot

trigger

All internal

functional reset

sources

configured for

short reset

cannot trigger

cannot

trigger

cannot

trigger

triggers

Whether BIST is executed or not depends on the chip configuration data stored in the shadow sector of the NVM.

End of the internal reset sequence (as specified in Table 30) can only be observed by release of RESET if it is not held low

externally beyond the end of the internal sequence which would prolong the internal reset PHASE3 till RESET is released

externally.

The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before. RESET

does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST disabled. However, it

can prolong these sequences if RESET is held low externally beyond the end of the internal sequence (beyond PHASE3).

If RESET is configured for long reset (default) and if BIST is enabled via chip configuration data stored in the shadow sector

of the NVM.

If RESET is configured for long reset (default) and if BIST is disabled via chip configuration data stored in the shadow

sector of the NVM.

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