PCM3168APAPR datasheet(12/66 Pages) TI1

12 / 66 page

PCM3168A

SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016

www.ti.com

Electrical Characteristics (continued)

At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit

data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL FILTER PERFORMANCE (12)

Group delay time (single, dual)

28/fS

sec

Group delay time (quad)

19/fS

sec

De-emphasis error

±0.1

POWER-SUPPLY REQUIREMENTS

VCCxx1/2

4.5

5.0

5.5

Voltage range

VDC

VDD1/2

3.0

3.3

3.6

fS = 48 kHz/ADC, fS = 48

162

210

kHz/DAC

ICC

fS = 96 kHz/ADC, fS = 192

162

kHz/DAC

Full power-down(13)

300

μA

Supply current

fS = 48 kHz/ADC, fS = 48

106

130

kHz/DAC

IDD

fS = 96 kHz/ADC, fS = 192

127

kHz/DAC

Full power-down(13)

μA

fS = 48 kHz/ADC, fS = 48

1160

1480

kHz/DAC

fS = 96 kHz/ADC, fS = 192

1230

kHz/DAC

Power dissipation

fS = 48 kHz/ADC, Power-

660

down/DAC

Power-down/ADC, fS = 48

633

kHz/DAC

Full power-down(13)

1.67

TEMPERATURE RANGE

PCM3168A Consumer

Operating temperature

–40

°C

grade

θJA

Thermal resistance

HTQFP-64

°C/W

(13) Halt SCKI, BCKAD, BCKDA, LRCKAD, and LRCKDA.

8.6 Timing Requirements: System Clock

Refer to Figure 1.

MIN

MAX

UNIT

tSCY

System clock pulse cycle time

tSCH

System clock pulse width high

tSCL

System clock pulse width low

tDTY

System clock pulse duty cycle

40%

60%

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