PCM3168APAPR datasheet(29/66 Pages) TI1

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MDI

(1)

'1'

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

Don'tCare(X)

W ADR6

MDO

Hi-Z

MDI

(1)

'0'

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

W ADR6

ADR6

R/W

RegisterAddress

RegisterData

ADR5

ADR4

ADR3

ADR2

ADR1

ADR0

MSB

LSB

PCM3168A

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SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016

9.3.11 Control Data Word Format

All single write/read operations through the serial control port use 16-bit data words. Figure 40 shows the control

data word format. The first bit is for read/write controls; 0 indicates a write operation and 1 indicates a read

operation. Following the first bit are seven other bits, labeled ADR[6:0] that set the register address for the

write/read operation. The eight least significant bits (LSBs), D[7:0] on MDI or MDO, contain the data to be written

to the register specified by ADR[6:0], or the data read from the register specified by ADR[6:0].

Figure 40. Control Data Word Format for MDI

9.3.12 Register Write Operation

Figure 41 shows the functional timing diagram for single write operations on the serial control port. MS is held at

a high state until a register must be written. To start the register write cycle, MS is set to a low state. 16 clocks

are then provided on MC, corresponding to the 16 bits of the control data word on MDI. After the 16th clock cycle

has been completed, MS is set high to latch the data into the indexed mode control register.

Also, the PCM3168A device supports multiple write operations in addition to single write operations, which can

be performed by sending the following N-times of the 8-bit register data after the first 16-bit register address and

accomplished by setting MS to a high state.

(1) X = Don't care

Figure 41. Register Write Operation

9.3.13 Register Read Operation

Figure 42 shows the functional timing diagram for single read operations on the serial control port. MS is held at

a high state until a register must be read. To start the register read cycle, MS is set to a low state. 16 clocks are

then provided on MC, corresponding to the first eight bits of the control data word on MDI and the second eight

bits of the read-back data word from MDO. After the 16th clock cycle has been completed, MS is held high for

the next write or read operation. MDO remains in a high impedance state except during the eight MC clock

periods of the actual data transfer.

(1) X = Don't care

Figure 42. Register Read Operation

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