PCM3168APAPR datasheet(28/66 Pages) TI1

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VDD

SynchronousClocks

ZERO

Power-Down

NormalOperation

SynchronousClocks

SCKI,

BCKAD/DA,

LRCKAD/DA

RST

InternalReset

VOUT1

VOUT8

DOUT1/2/3

ADCDLY2

DACDLY1

DACDLY2

0.5

VCC

(VDD=3.3V,typ)

3846

SCKI

Fade-In

100ns(min)

ADCDLY1

PCM3168A

SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016

www.ti.com

The PCM3168A device does not require particular power-on sequences for VCC and VDD; it allows VDD on and

then VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings, however,

simultaneous power-on is recommended for avoiding unexpected responses on VOUTx and DOUTx. Figure 2

illustrates the response for VCC on with VDD on.

Figure 39. External Reset Timing Requirements

9.3.7 Highpass Filter (HPF)

The PCM3168A device includes a highpass filter (HPF) for all ADC channels in order to remove the DC

component of the digitized input signal. The filter is located at the output of the digital decimation filter. The –3-dB

corner frequency for the HPF scales with the output sampling rate, where f–3 dB = 0.020 × fS/1000. When

fS = 48 kHz, f–3 dB is 0.96 Hz. The HPF function can be disabled (bypassed) by the BYP bits in two channels.

9.3.8 Overflow Flag

The PCM3168A device includes an overflow flag output for all ADC channels. As soon as any of the six-channel

ADC digital outputs exceed the full-scale range, an overflow flag is forced high on the OVF pin. The overflow flag

is held high for 1024 LRCKAD clock cycles. In parallel, overflow flag information is stored in the OVF bits of the

mode control register, and the OVF bit is held until the mode control register is read. The overflow flag polarity

can be changed by the OVFP bit. The OVF pin also indicates internal reset completion by transmitting a 4096

SCKI width pulse.

9.3.9 Zero Flag

The PCM3168A device includes a zero flag output for all DAC channels. When all of the eight-channel DACs

digital inputs have continued as zero data for 1024 LRCKDA clock cycles, the zero flag is forced high on ZERO.

In parallel, zero flag information is stored in the ZERO bits according to channel. The zero flag polarity can be

changed by the ZREV bit. Also, the zero flag function can be selected by the AZRO bits. AND or OR logic for

stereo, six channels, and eight channels can be selected.

9.3.10 Four-Wire (SPI) Serial Control

The PCM3168A device includes an SPI-compatible serial port that operates asynchronously with the audio serial

interface.

The

control

interface

consists

MDI/SDA/DEMP,

MDO/ADR1/MD1,

MC/SCL/FMT,

and

MS/ADR0/MD0. MDI is the serial data input to program the mode control registers. MDO is the serial data output

to read back register settings and some flags. MDO is inactive (Hi-Z, high impedance) during MS = high. MC is

the serial bit clock that shifts the data into the control port. MS is the select input to enable the mode control port.

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