MT9079AC datasheet(9/54 Pages) MITEL

9 / 54 page

MT9079

4-245

don't care, CAR data D7 - D0 = page number).

Second, each page has a maximum of 16 registers

that are addressed on a read or write to a non-CAR

address (non-CAR: address AC4 = 1, AC3-AC0 =

memory is selected, it is only necessary to write to

the CAR when a different page is to be accessed.

See Figure 17 for timing requirements.

Communications between a serial controller and

MT9079

two

byte

operations.

First,

Command/Address byte selects the address and

operation that follows. That is, the R/W bit selects a

read or write function and A4 determines if the next

byte is a new memory page address (A4 = 0) or a

data transfer within the current memory page (A4 =

1). The second byte is either a new memory page

address (when A4 = 0) or a data byte (when A4 = 1).

This is illustrated as follows:

a) Command/Address byte -

where:

R/W

- read or write operation,

- no function,

A4 = 0 - new memory page address to follow,

A4 = 1 - data byte to follow, and

A3-A0 - determines the byte address.

R/W

b) Page address or data byte -

See Figures 18 and 19 for timing requirements.

Table 2 associates the MT9079 control and status

pages with access and page descriptions, as well as

an ST-BUS stream. When ST-BUS access mode is

used, each page contains 16 registers that are

associated consecutively with the first or second 16

channels of each ST-BUS stream. That is, page 1

time slots 0 to 15, and page

2 register locations

10000 to 11111 appear on CSTi0 time slots 16 to 31.

It should be noted that access to the transmit and

receive circular buffers is not supported in ST-BUS

mode.

Common ST-BUS Streams

There are several control and

status

ST-BUS

streams that are common to all modes. CSTo1

contains the received channel associated signalling

bits (e.g., CCITT R1 and R2 signalling), and when

control bit RPSIG = 0, CSTi2 is used to control the

transmit channel associated signalling. DSTi and

DSTo contain the transmit and receive voice and

digital data. Figures 4a, b and c illustrate the relative

Page Address

D7 - D0

Processor/

Controller

Access

ST-BUS

Access

00000001

Master

Control

R/W

CSTi0

00000010

R/W

00000011

Master

Status

RCSTo0

00000100

R/W

00000101

Per Channel Transmit Signalling

R/W

CSTi2

00000110

Per Channel Receive Signalling

CSTo1

00000111

Per Time Slot

Control

R/W

CSTi1

00001000

R/W

00001001

Transmit Circular Buffer Zero

R/W

---

00001010

Transmit Circular Buffer One

R/W

---

00001011

Receive Circular Buffer Zero

---

00001100

Receive Circular Buffer One

---

00001101

Transmit National Bit Buffer

R/W

---

00001110

Receive National Bit Buffer

---

Table 2 - Register Summary

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