ZL6105ALAF datasheet(15/35 Pages) INTERSIL

15 / 35 page

ZL6105

FN6906.5

December 19, 2013

Power-Good

The ZL6105 provides a Power-Good (PG) signal that indicates the

output voltage is within a specified tolerance of its target level

and no fault condition exists. By default, the PG pin will assert if

the output is within -10% of the target voltage. These limits and

the polarity of the pin may be changed via the I2C/SMBus

interface. See Application Note AN2033 for details.

A PG delay period is defined as the time from when all conditions

within the ZL6105 for asserting PG are met to when the PG pin is

actually asserted. This feature is commonly used instead of using

an external reset controller to control external digital logic. By

default, the ZL6105 PG delay is set equal to the soft-start ramp

time setting. Therefore, if the soft-start ramp time is set to 10ms,

the PG delay will be set to 10ms. The PG delay may be set

independently of the soft-start ramp using the I2C/SMBus as

described in Application Note AN2033.

If Auto Comp is enabled, the PG timing is further controlled by

the PG Assert parameter, as described in “Loop Compensation”

on page 21.

Switching Frequency and PLL

The ZL6105 incorporates an internal phase-locked loop (PLL) to clock

the internal circuitry. The PLL can be driven by an external clock source

connected to the SYNC pin. When using the internal oscillator, the SYNC

pin can be configured as a clock source for other Zilker Labs devices.

The SYNC pin is a unique pin that can perform multiple functions

depending on how it is configured. The CFG1 pin is used to select

the operating mode of the SYNC pin as shown in Table 9.

Figure 13 illustrates the typical connections for each mode.

CONFIGURATION A: SYNC OUTPUT

When the SYNC pin is configured as an output (CFG1 pin is tied HIGH),

the device will run from its internal oscillator and will drive the resulting

internal oscillator signal (preset to 400kHz) onto the SYNC pin so other

devices can be synchronized to it. The SYNC pin will not be checked for

an incoming clock signal while in this mode.

CONFIGURATION B: SYNC INPUT

When the SYNC pin is configured as an input (CFG1 pin is tied LOW) and

the device is in Monitor Mode or self-enabled (EN tied to V25 or

ON_OFF_CONFIG[4] = 0), the device will check for a clock signal on the

SYNC pin immediately after power-up. In this case, the incoming clock

signal must be in the range of 200kHz to 1.4MHz and must be stable

within 10µs after V25 rises above 2.25V. When the SYNC pin is

configured as an input (CFG1 pin is tied LOW) and the device is in Low

Power Mode, the device will check for a clock signal on the SYNC pin

immediately after EN goes true. In this case, the incoming clock signal

must be in range and stable before EN goes true. The ZL6105's

oscillator will then synchronize with the rising edge of the external clock.

The incoming clock signal must be in the range of 200kHz to

1.4MHz and must be stable when the enable pin is asserted. The

clock signal must also exhibit the necessary performance

requirements (see “Electrical Specifications” on page 8). In the

event of a loss of the external clock signal, the output voltage

may show transient over/undershoot.

If this happens, the ZL6105 will automatically switch to its

internal oscillator and switch at a frequency close to the previous

incoming frequency.

CONFIGURATION C: SYNC AUTO DETECT

When the SYNC pin is configured in auto detect mode (CFG1 pin is left

OPEN) and the device is in Monitor Mode or self-enabled (EN tied to V25

or ON_OFF_CONFIG[4] = 0), the device will check for a clock signal on

the SYNC pin immediately after power-up. In this case, the incoming

clock signal must be in the range of 200kHz to 1.4MHz and must be

stable within 10µs after V25 rises above 2.25V. When the SYNC pin is

configured in auto detect mode (CFG1 pin is left OPEN) and the device is

in Low Power Mode, the device will check for a clock signal on the SYNC

pin immediately after EN goes true. In this case, the incoming clock

signal must be in range and stable before EN goes true.

If a clock signal is present, the ZL6105's oscillator will then

synchronize with the rising edge of the external clock. Refer to

“Configuration B: SYNC INPUT” in the preceding section.

If no incoming clock signal is present, the ZL6105 will configure

the switching frequency according to the state of the SYNC pin as

listed in Table 10. In SYNC AutoDetect mode, the ZL6105 will

only read the SYNC pin connection during the first start-up

sequence; changes to SYNC pin connections will not affect fSW

until the power (VDD) is cycled off and on.

If the user wishes to run the ZL6105 at a frequency not listed in

Figure 10, the switching frequency can be set using an external

resistor, RSYNC, connected between SYNC and SGND using Table 11.

TABLE 8. MINIMUM TON DELAY vs OPERATING MODE

Current

Sharing

AutoComp

Low-Power

Standby

Min.

TON_DELAY

(ms)

Disabled

False

Disabled

Enabled

False

Disabled

True

Enabled

Disabled

True

Enabled

TABLE 9. SYNC PIN FUNCTION SELECTION

CFG1 PIN

SYNC PIN FUNCTION

LOW

SYNC is configured as an input

OPEN

Auto Detect mode

HIGH

SYNC is configured as an output

fSW = 400kHz

TABLE 10. SWITCHING FREQUENCY PIN-STRAP SETTINGS

SYNC PIN

FREQUENCY

LOW

200kHz

OPEN

400kHz

HIGH

1MHz

Resistor

See Table 11

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