ZL6105ALAF datasheet(12/35 Pages) INTERSIL

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ZL6105

FN6906.5

December 19, 2013

Power Conversion Functional

Description

Internal Bias Regulators and Input Supply

Connections

The ZL6105 employs two internal low dropout (LDO) regulators to

supply bias voltages for internal circuitry, allowing it to operate

from a single input supply. The internal bias regulators are as

indicated in the following:

VR - The VR LDO provides a regulated 5V bias supply for the

MOSFET driver circuits. It is powered from the VDD pin. A 4.7µF

filter capacitor is required at the VR pin.

V25 - The V25 LDO provides a regulated 2.5V bias supply for

the main controller circuitry. It is powered from an internal 5V

node. A 10µF filter capacitor is required at the V25 pin.

When the input supply (VDD) is higher than 5.5V, the VR pin should

not be connected to any other pins. It should only have a filter

capacitor attached as shown in Figure 8. Due to the dropout voltage

associated with the VR bias regulator, the VDD pin must be

connected to the VR pin for designs operating from a supply below

5.5V. Figure 8 illustrates the required connections for both cases.

Note: the internal bias regulators are not designed to be outputs

for powering other circuitry. Do not attach external loads to any of

these pins. The multi-mode pins may be connected to the V25

pin for logic HIGH settings.

High-side Driver Boost Circuit

The gate drive voltage for the high-side MOSFET driver is

generated by a floating bootstrap capacitor, CB (see Figure 5).

When the lower MOSFET (QL) is turned on, the SW node is pulled

to ground and the capacitor is charged from the internal VR bias

regulator through diode DB. When QL turns off and the upper

MOSFET (QH) turns on, the SW node is pulled up to VDD and the

voltage on the bootstrap capacitor is boosted approximately 5V

above VDD to provide the necessary voltage to power the

high-side driver. A Schottky diode should be used for DB to help

maximize the high-side drive supply voltage.

Output Voltage Selection

STANDARD MODE

The output voltage may be set to any voltage between 0.6V and

5.0V provided that the input voltage is higher than the desired

output voltage by an amount sufficient to prevent the device

from exceeding its maximum duty cycle specification. Using the

pin-strap method, VOUT can be set to any of nine standard

voltages as shown in Table 2.

The resistor setting method can be used to set the output voltage

to levels not available in Table 2. Resistors R0 and R1 are

selected to produce a specific voltage between 0.6V and 5.0V in

10mV steps. Resistor R1 provides a coarse setting and resistor

R0 provides a fine adjustment, thus eliminating the additional

errors associated with using two 1% resistors (this typically adds

approximately 1.4% error).

To set VOUT using resistors, follow the steps indicated to calculate

an index value and then use Table 3 to select the resistor that

corresponds to the calculated index value as follows:

1. Calculate Index1:

2. Round the result down to the nearest whole number.

3. Select the value of R1 from Table 3 using the Index1 rounded

value from step 2.

4. Calculate Index0:

5. Select the value of R0 from Table 3 using the Index0 value

from step 4.

Example from Figure 9: For VOUT = 1.33V,

Index1 = 4 x 1.33V = 5.32;

From Table 3, R1 = 16.2kΩ

Index0 = (100 x 1.33V) – (25 x 5) = 8;

From Table 3, R0 = 21.5kΩ

VIN

VDD

VIN

VDD

3V ≤VIN ≤ 5.5V

5.5V <VIN ≤ 14V

FIGURE 8. INPUT SUPPLY CONNECTIONS

TABLE 2. OUTPUT VOLTAGE PIN-STRAP SETTINGS

LOW

OPEN

HIGH

LOW

0.6V

0.8V

1.0V

OPEN

1.2V

1.5V

1.8V

HIGH

2.5V

3.3V

5.0V

TABLE 3. OUTPUT VOLTAGE RESISTORS SETTINGS

INDEX

R0 OR R1

Ω)INDEX

R0 OR R1

Ω)

34.8

38.3

12.1

42.2

13.3

46.4

414.7

51.1

16.2

56.2

617.8

61.9

19.6

68.1

821.5

23.7

82.5

26.1

90.9

28.7

100

31.6

Index1 = 4 x VOUT (VOUT in 10mV steps)

(EQ. 2)

Index0 = 100 x VOUT - (25 x Index1)

(EQ. 3)

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