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DM385 bảng dữ liệu(PDF) 85 Page - Texas Instruments

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tên linh kiện DM385
Giải thích chi tiết về linh kiện  DM385 and DM388 DaVinci??Digital Media Processor
PDF  281 Pages
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nhà sản xuất  TI [Texas Instruments]
Trang chủ  http://www.ti.com
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DM385 bảng dữ liệu(HTML) 85 Page - Texas Instruments

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DM385, DM388
www.ti.com
SPRS821D – MARCH 2013 – REVISED DECEMBER 2013
3.3.15 PCI Express (PCIe)
Table 3-33. PCI Express (PCIe) Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
PCIE_RXN0
PCIE Receive Data Lane 0. When the PCIe SERDES are I
J30
powered down, these pins should be left unconnected.
PCIE_RXP0
PCIE Receive Data Lane 0. When the PCIe SERDES are I
K30
powered down, these pins should be left unconnected.
PCIE_TXN0
PCIE Transmit Data Lane 0. When the PCIe SERDES
O
K31
are powered down, these pins should be left
unconnected.
PCIE_TXP0
PCIE Transmit Data Lane 0. When the PCIe SERDES
O
L31
are powered down, these pins should be left
unconnected.
SERDES_CLKN
PCIE Serdes Reference Clock Inputs. When PCIe is not
I
H31
used these pins can be left unconnected.
SERDES_CLKP
PCIE Serdes Reference Clock Inputs. When PCIe is not
I
H30
used these pins can be left unconnected.
NOTE
PCIe is supported on all DM385 devices and also on DM388 devices with PCIe enabled. For
DM388 devices with PCIe disabled, the pins in Table 3-33 should be left unconnected.
Copyright © 2013, Texas Instruments Incorporated
Device Pins
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