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UPD75P4308GS bảng dữ liệu(PDF) 15 Page - NEC |
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UPD75P4308GS bảng dữ liệu(HTML) 15 Page - NEC |
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15 / 60 page ![]() µPD75P4308 15 6. MEMORY CONFIGURATION Figure 6-1. Program Memory Map MBE MBE MBE MBE MBE MBE MBE RBE RBE RBE RBE RBE RBE RBE 0 0 0 0 0 0 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) INT0 start address (upper 5 bits) INT0 start address (lower 8 bits) INT1 start address (upper 5 bits) INT1 start address (lower 8 bits) INTCSI start address (upper 5 bits) INTCSI start address (lower 8 bits) INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) INTT1 start address (upper 5 bits) INTT1 start address (lower 8 bits) Reference table for GETI instruction 0000H 0002H 0004H 0006H 0008H 000AH 000CH 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH CALLF !faddr instruction entry address Branch address for the following instructions Branch/call address by GETI BR $addr instruction relative branch address (–15 to –1, +2 to +16) BRCB !caddr instruction branch address BRCB !caddr instruction branch address 7 6 50 • BR BCDE • BR BCXA • BR !addr • CALL !addr • BRA !addr1 • CALLA !addr1 Note Note 0020H Note Can be used only in the Mk II mode. Remark For instructions other than those noted above, the “BR PCDE” and “BR PCXA” instructions can be used to branch to addresses with changes in the PC’s lower 8 bits only. |
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