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UPD75P4308GS bảng dữ liệu(PDF) 33 Page - NEC |
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UPD75P4308GS bảng dữ liệu(HTML) 33 Page - NEC |
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33 / 60 page ![]() µPD75P4308 33 System Clock Oscillation Circuit Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5. V) Resonator Recommended Parameter Conditions MIN. TYP. MAX. Unit constants Ceramic Oscillation frequency 1.0 6.0Note 3 MHz resonator (fX)Note 1 Oscillation After VDD has 4 ms stabilization timeNote 2 reached MIN. value of oscillation voltage range Crystal Oscillation frequency 1.0 6.0Note 3 MHz resonator (fX)Note 1 Oscillation VDD = 5.0 V ± 10 % 10 ms stabilization timeNote 2 30 ms External X1 input frequency 1.0 6.0Note 3 MHz clock (fX)Note 1 X1 input high-, 83.3 500 ns low-level widths (tXH, tXL) Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation circuit only. For the instruction execution time, refer to AC Characteristics. 2. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode. 3. When the oscillation frequency fX satisfies 4.19 MHz < fX ≤ 6.0 MHz at 1.8 V ≤ VDD < 2.7 V, do not set PCC = 0011 as an instruction execution time. If PCC = 0011 is selected, one machine cycle takes less than 0.95 µs, and the MIN. value rating of 0.95 µs is not satisfied. Caution When using the system clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: · Keep the wiring length as short as possible. · Do not cross the wiring with other signal lines. · Do not route the wiring in the vicinity of a line through which a high alternating current flows. · Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS. Do not ground to a ground pattern through which a high current flows. · Do not extract signals from the oscillation circuit. X1 X2 X1 X2 C1 C2 X1 X2 C1 C2 |
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