UPD75P4308GS datasheet(38/60 Pages) NEC

38 / 60 page

µPD75P4308

AC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

tCY

Operates with

VDD = 2.7 to 5.5 V

0.67

µs

system clock

0.95

µs

TI0, TI1 input frequency

fTI

VDD = 2.7 to 5.5 V

MHz

275

kHz

TI0, TI1 input high-,

tTIH, tTIL

VDD = 2.7 to 5.5 V

0.48

µs

low-level widths

1.8

µs

Interrupt input high-,

tINTH, tINTL

INT0

IM02 = 0

Note 2

µs

low-level widths

IM02 = 1

INT1, 2, 4

µs

KR0-7

µs

RESET low-level width

tRSL

µs

Notes 1. The cycle time (minimum instruction

execution time) of the CPU clock (

Φ) is

determined by the oscillation frequency

of the connected resonator and proces-

sor clock control register (PCC).

The figure on the right shows the supply

voltage VDD vs. cycle time tCY character-

istics when the device operates with the

system clock.

2. 2tCY or 128/fX depending on the setting

of the interrupt mode register (IM0).

CPU clock cycle timeNote 1

(minimum instruction execution

time = 1 machine cycle)

0.5

(with system clock)

tCY vs VDD

Operation guaranteed range

Supply voltage VDD [V]

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