UM0843 datasheet(19/48 Pages) STMICROELECTRONICS

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UM0843

Block descriptions

Doc ID16543 Rev 2

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The other option is to use the external clock and sync signals, in this case, it act as TDM

slave, it is necessary to remove connection between JP5 with JP6, and then plug the related

external clock and sync signals cables to connectors: JP5.

By default the external clocks and syncs jumpers configuration of HDLC-TDM slave is

selected as shown in Table 14

Table 13.

HDLC-TDM master on-board clock settings

Jumper

Description

Configuration

JP6

Supply on-board clocks and syncs

Default: output TDM_RSYNC(JP6-6),

TDM_RCLK(JP6-8), TDM_TSYNC(JP6-10) and

TDM_TCLK(JP6-12)

TDM_RCLK,TDM_TCLK: 8.192MHz

TDM_RSYNC, TDM_TSYNC: 8 kHz

JP5-13 and JP6-13 are ground.

JP5

Receive clocks and syncs to SPEAr for HDLC-

TDM.

Default: input TDM_RSYNC(JP5-6),

TDM_RCLK(JP5-8), TDM_TSYNC(JP5-10) and

TDM_TCLK(JP5-12,)

Red wire: connect JP6 to JP5

Blue wire: output clocks and syncs to others slave

boards

JP5-2

Input HDLC-TDM RXD to SPEAr, it needs to be

connected to the TXD signal of other HDLC-TDM

slave boards.

JP5-4

Output HDLC-TDM TXD from SPEAr to RXD signal

of other HDLC-TDM slave boards.

Table 14.

HDLC-TDM slave external clock and sync settings

Jumper

Description

Configuration

JP5

Receive clocks and syncs to CPU for HDLC-TDM from

external boards.

Default: input TDM_RSYNC(JP6-6), TDM_RCLK(JP6-8),

TDM_TSYNC(JP6-10) and TDM_TCLK(JP6-12)

TDM_RCLK,TDM_TCLK: 8.192MHz

TDM_RSYNC, TDM_TSYNC: 8KHz

JP5-13 is ground.

Red wire: input clocks and syncs from other HDLC_TDM

slave boards

JP5-2

Input HDLC-TDM RXD to CPU, it needs to be connected to

TXD signal of other HDLC-TDM slave boards.

JP5-4

Output HDLC-TDM TXD from CPU to RXD signal of other

HDLC-TDM slave boards.

JP5

JP6

1 2

JP5

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