UM0843 datasheet(18/48 Pages) STMICROELECTRONICS

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Block descriptions

UM0843

18/48

Doc ID16543 Rev 2

6.6

HDLC-E1/TDM

There is one HDLC-E1/TDM on the board, it features two modes: HDLC-E1 and HDLC-

TDM.

For HDLC-E1 mode, it uses E1 PHY(U6, DS21354) to communicate with other boards or

systems, the connectors are J4 (E1-Receiver), J2 (E1-Transmit) and J3 (RJ48 includes

TXD/RXD). The software has to read and write to the E1 PHY registers via the EMI bus to

initialize, configure and control the E1 PHY.

For HDLC-E1 mode to function properly, it is has to be driven by the external clocks (TCLK,

RCLK) and external sync (RSYNC,TSYNC). The clock frequency is 2.048 MHz, the sync

frequency is 8 kHz. The default setting is to use the on-board clocks and syncs that are

generated by the E1 PHY (U36).

For HDLC-TDM mode, no PHY is required and the 128 time slot TDM signals are

transmitted to and received from other boards or systems via the J5 connector. For HDLC-

TDM mode to function properly, it is has to be driven by the external clocks (TCLK, RCLK)

and external sync (RSYNC,TSYNC). The clock frequency is 8.192 MHz, the sync frequency

is 8 kHz.

There are two ways to deliver the clocks and syncs to the SPEAr. The default option is to

use the on-board clocks (8.192 MHz) and syncs (8 kHz) that are generated by the U38

CPLD, in this case, it act as TDM master. At the same time, it can also provide these source

clocks and syncs to other TDM slave boards or systems.

By default the on-board clocks and sync configuration of HDLC-TDM is selected as shown

in Table 13

Table 12.

HDLC-RS485-2 external clock jumper settings

Jumper

Description

Configuration

JP62

Supply on-board clocks or

external clocks to CPU for

HDLC-RS485-2 TCLK.

Setting: to use external clocks

(PIN-2)

JP63

Supply on-board clocks or

external clocks to CPU for

HDLC-RS485-2 RCLK.

Setting: to use external clocks

(PIN-2)

JP64

Signal Ground

TCLK

RCLK

GND

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