AN3422 datasheet(50/52 Pages) STMICROELECTRONICS

50 / 52 page

Firmware migration using the library

AN3422

50/52

Doc ID 018976 Rev 2

5.8

Backup data registers

In STM32F1 series the Backup data registers are managed through the BKP peripheral,

while in L1 series they are a part of the RTC peripheral (there is no BKP peripheral).

The example below shows how to write to/read from Backup data registers in STM32F1

series:

uint16_t BKPdata = 0;

...

/* Enable APB2 interface clock for PWR and BKP */

RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);

/* Enable write access to Backup domain */

PWR_BackupAccessCmd(ENABLE);

/* Write data to Backup data register 1 */

BKP_WriteBackupRegister(BKP_DR1, 0x3210);

/* Read data from Backup data register 1 */

BKPdata = BKP_ReadBackupRegister(BKP_DR1);

In L1 series you have to update this code as follows:

uint16_t BKPdata = 0;

...

/* PWR Clock Enable */

RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);

/* Enable write access to RTC domain */

PWR_RTCAccessCmd(ENABLE);

/* Write data to Backup data register 1 */

RTC_WriteBackupRegister(RTC_BKP_DR1, 0x3220);

/* Read data from Backup data register 1 */

BKPdata = RTC_ReadBackupRegister(RTC_BKP_DR1);

The main changes in the source code in L1 series vs. F1 are described below:

There is no BKP peripheral

Write to/read from Backup data registers are done through RTC driver

Backup data registers naming changed from BKP_DRx to RTC_BKP_DRx, and

numbering starts from 0 instead of 1

AN3422 bảng dữ liệu(PDF) 50 Page - STMicroelectronics