AN3307 datasheet(27/37 Pages) STMICROELECTRONICS

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AN3307

Class B solution structure

Doc ID 18186 Rev 4

27/37

Note:

The RAM test is byte oriented but the more precise bit March testing algorithm can be used,

too. This method is more time and code consuming.

5.2.5

Clock startup self-test

The flow chart diagram of the test is shown in Figure 12. It expresses the principle of the

method, graphically. Initially the internal low speed clock (LSI) source is started. The

external high speed source (HSE) is started in the next step. The CPU is still running on the

internal high speed clock source (HSI). The system timer (SysTick) is started with the HSI

clock source while the RTC system runs on the LSI clock source. One complete underflow

cycle of the SysTick timer is performed. The number of LSI periods counted in that cycle

gives the HSI ratio value (number of HSI pulses within the interval corresponding to one LSI

period). This initial HSI ratio measurement is stored as a reference for the next runtime

measurements.

Figure 12.

Clock startup self-test subroutine structure

In the next step, the external HSE clock is switched as the new clock source for the SysTick

timer. Another complete underflow cycle of SysTick timer is performed. The number of LSI

periods counted in this cycle gives the HSE ratio (number of HSE pulses in the interval

corresponding to one LSI period). The HSE value is then computed from the known HSI

value and both HSI and HSE ratios measured. If the HSE value deviates from the expected

Start of LSI clock

Start of H SE clock

Test OK

F ail Safe rou tine

Fail

M ea sure LSI versus H SI

Sw itch clock from H SI t o H SE

Fail

M ea sure LSI versus H SE

H SE in range

+/- 25% ?

Fail

Yes

Sw itch clock from H SE to H SI

Run RT C(LSI) & SysT ick (HSI)

=> H SI R ef R atio

HSE= (H SI * HSI Ref Ratio) / HSE Ratio

=> H SE R atio

Run RT C(LSI) & SysT ick (HSE)

MS18598V1

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