AN3307 datasheet(12/37 Pages) STMICROELECTRONICS

12 / 37 page

Compliance with IEC and VDE standards

AN3307

12/37

Doc ID 18186 Rev 4

Users can include a part or all of these software modules certified by VDE into the project. If

they stay unchanged and are integrated in accordance with the guidelines, the time and

costs needed for a certified end-application would be significantly reduced.

Note:

If minor changes have to be made to the modules, it is suggested that you keep careful track

of all of these changes in order to inform the certification authority of all modifications made

to the certified routines.

Table 2.

Overview of methods used in the micro-specific tests provided with this

application note

Components to be

verified

Method used

CPU registers

Functional test of all registers and flags including R13 (stack pointer), R14

(link register) and PSP (Process stack pointer) is done at startup. In the

runtime test R13, R14, PSP and flags are not tested. The stack pointer is

tested for underflow and overflow, the link register is tested by PC

monitoring. If any error is found, the software jumps directly to the Fail Safe

routine

Program counter

Two different watchdogs driven by two independent clock sources can

reset the device when the program counter is lost. The Window watchdog,

driven by the main oscillator, performs time slot monitoring while the

Independent one, driven by the low speed internal RC oscillator, is

impossible to disable once enabled. Both watchdogs must be serviced at

regular intervals. Program control flow is additionally monitored using a

specific software method.

Addressing and data

path

This is tested indirectly by RAM functional and Flash integrity tests, stack

overflow (a specific pattern is written at a low boundary of stack space and

checked for corruption at regular intervals) and underflow (a second

pattern is written at a high boundary if it is not at the RAM end). In addition,

a bus error exception vector is fetched by the CPU if a memory access

fault occurs.

Clock

A reciprocal method of comparing two independent clock sources is used

while clocking two timers. Wrong main frequency (harmonic/sub harmonic)

can be detected using the external low speed 32kHz oscillator as a

timebase.

Non-volatile memory

A 16-bit CRC software checksum test of the entire memory is done at

startup and a partial memory test is repeated at runtime (block by block).

Optionally the built in hardware for fast 32-bit CRC calculation can be used.

Volatile memory

A March C- (or optionally March X) full memory test is done at startup and

a partial memory test is repeated at runtime (block by block), scrambled

order of physical addresses in RAM is respected in tests for optimal

coverage of coupling faults, word protection with double redundancy

(inverse values stored in non adjacent memory space) is used for safety

critical Class B variables, Class A variable space, stack and unused space

are not tested at runtime.

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