Class B solution structure

AN3307

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Doc ID 18186 Rev 4

5.2.2

Watch dog startup self-test

The structure of the test is based on the reset status register content which registers all the

previous reset causes by setting different flags (see Figure 8).

Figure 8.

Watchdog startup self-test structure

The standard reset condition (power on, low power, software or external pin flag indicates

the previous reset cause) is assumed at the beginning of the watchdog test. All the flags are

cleared, the IWDG timeout is set to the shortest period so an IWDG reset should then occur.

After the next reset, the IWDG flag should be set and recognized as the sole reset cause.

The test can then continue with the WWDG test. When both flags are set in reset status

register, the test is considered as completed and all the flags in the reset status register are

cleared again.

Users must take care to set both IWDG and WWDG periods properly. Their periods and the

a normal refresh is performed at the successful end of the periodic runtime test in the main

loop.

c.

The system tick interrupt service routine indicates a defined time base interval via a dedicated time base flag.

The run-time test is started at the main level periodically at this interval. As the watchdog control is the last step

of successfully finished run-time tests (and it should be the only place where the watchdog is refreshed in the

main loop) the time base interval must be set in correlation with the watchdog timeout and vice versa. The

watchdog refresh period must be shorter than the watchdog timeout to prevent a reset of the CPU. Refer to the

flowchart in Figure 15.

MS18595V1

IWDG

reset ?

Clear All Flags

Test IWDG

Test WWDG

WWDG

reset ?

Clear All Flags

Test OK

No

No

Yes

Yes

HW Reset

HW Reset

Standard

reset?

Yes

Yes

No

Software Reset

SW Reset