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AN3137 bảng dữ liệu(PDF) 33 Page - STMicroelectronics

tên linh kiện AN3137
Giải thích chi tiết về linh kiện  Analog-to-digital converter on STM8L and STM8AL devices
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AN3137 bảng dữ liệu(HTML) 33 Page - STMicroelectronics

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AN3137
Methods for precision improvement
Doc ID 16983 Rev 3
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4.4.4
Source of described problem - ADC design
The following sections list some possible causes for the charging of the internal sampling
capacitor Csh. This is not an exhaustive list; only the main possible sources of the ADC
design are listed.
Parasitic switch capacitance effect
The sampling switch inside ADC sampling circuit (see Figure 14) is not ideal. In reality the
sample and hold switch (S1) is designed as 2 transistors (PMOS and NMOS):
Figure 18.
Implementation of sampling switch
The switch is controlled by the gate voltages of transistors (inverted signal on PMOS
transistor). This design is a standard bidirectional switch (for rail to rail range of input Uin
voltages).
Both transistors have parasitic capacitances between gate and source. If those
capacitances are charged (close to the switch), then their charge can be transferred to the
sampling capacitor.



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