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AN2834

How to get the best ADC accuracy

3.4.3

Minimizing added errors

Workaround for high impedance sources

To solve the added error problem, you can increase the sampling time (TS) configuring ADC

settings in MCU firmware, so that you discharge the Csh charge through the source

impedance Rin. The time constant (Rin * Csh) is the reference for choosing the sampling

time. To choose the sampling time cycles, use this formula (for max. error of 1/2 lsb, see

also Section 3.2.6):

The clock for ADC (fADC) is another important factor; slowing down the ADC clock increases

the sampling time.

Figure 35. Effect of sampling time extension

If the maximum register value of the sampling time (TS) setting is reached and the problem

is still present, you need a more complex solution which is applicable also for

measurements of source with extra high internal impedance (see the section Workaround

for extra high impedance sources below).

Note that for this application you must take into account not only the internal sampling

capacitance, but also any external parasitic capacitance (in parallel to Cext), such as: pin

capacitance, PCB path capacitance, etc.

Do not add any external capacitor (Cext) to the input pin when applying this above

workaround. Its capacity will increase the timing constant (Rin * Csh || Cext) and the problem

will remain.

TS fADC Rin Csh









cycles



Original sampling

time (tS)

Conversion time

(tC)

Extended sampling

ai17907

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