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Giải thích chi tiết về linh kiện  How to get the best ADC accuracy in STM32Fx Series and STM32L1 Series devices
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AN2834
ADC errors
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2.1.2
Gain error
Gain error is defined as the deviation between the last actual transition and the last ideal
transition. Gain error is represented as EG.
The last actual transition is the transition from FFEh to FFFh. Ideally, there should be a
transition from FFEh to FFFh, when the analog input is equal to VREF+ – 0.5LSB. So for
VREF+= 3.3 V, the last ideal transition should be at 3.299597 V.
If the ADC provides the FFFh reading for VAIN < VREF+ – 0.5LSB, then we have a negative
gain error.
Example
Gain error EG = Last actual transition – ideal transition
If VREF+ = 3.3 V and VAIN = 3.298435 V generates a transition from FFE to FFF then,
EG = 3.298435 V – 3.299597 V
EG = –1162 µV
EG = (–1162 µV / 805.6 µV) LSB = –1.44 LSB
If we do not get a full scale reading (FFFh) for VAIN equal to VREF+, the gain error is positive.
This means that a voltage greater than VREF+ will cause the last transition. Figure 9 shows a
positive gain error and Figure 10, a negative gain error.
Figure 9. Positive gain error representation
Figure 10. Negative gain error representation
VAIN
Digital output
ai15477
Ideal transfer curve
Actual transfer curve
EG > 0
4095
4094.5
LSB
VAIN
Digital output
ai15478
Ideal transfer curve
Actual transfer curve
EG < 0
4095
4094.5
LSB



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