AN2633 datasheet(5/48 Pages) STMICROELECTRONICS

5 / 48 page

AN2633

Power supply and clocks

5/48

1.1.2

Independent A/D converter supply and reference voltage

The ADC has an isolated power supply which you can separately filter and shield from noise

in the PCB.

On 128-pin and 144-ball packages, the ADC unit has an independent analog voltage supply

input at pin AVDD (the ADC current consumption is detailed in Section 3.3: Measurements

and typical values on page 41) to accept a very clean voltage source. Additionally, an

independent supply ground connection is provided on pin AVSS. You can connect a separate

external reference voltage input for ADC on the AVREF pin for better accuracy on low

voltages inputs. The voltage on AVREF can range from 1.0 V to VDDQ.

On 80-pin/ball packages, the ADC voltage supply is tied internally to the ADC reference

voltage pin AVCC_AVREF and the analog ground is shared with the digital ground at a single

point, on pin AVSS_VSSQ.

1.1.3

Battery supply

An optional stand-by voltage from a battery or other source may be connected to pin VBATT

to retain the contents of SRAM in the event of a loss of the main digital supplies (VDD and

VDDQ). The SRAM will automatically switch its supply from the internal VDD source to the

VBATT pin when the VDD and VDDQ voltage drops below the LVD threshold (and VBAT

remains above the threshold).

Note:

In order to use the battery supply, the LVD must be enabled.

The VBATT pin also supplies power to the RTC unit, allowing the RTC to function even when

the main digital supplies (VDD and VDDQ) are switched off. By programming the device

configuration via JTAG, you can select to power only the RTC (by configuring the RTC) or

both the SRAM (by enabling the PWR bit in the RTC_CR register) and the RTC from VBATT.

1.1.4

Low voltage detector (LVD)

Voltage dropout: The LVD circuit monitors VDD, and VDDQ supplies and generates a global

reset whenever either voltage drops below the configured VDD_LVD and VDDQ_LVD levels. If

the MCU was reset by the LVD, this is flagged in the System status register

(SCU_SYSSTATUS) and an interrupt request to the VIC is generated if enabled.

Voltage brownout: You can also program the LVD to generate an Early Warning interrupt

when either voltage drops below the VDD_BRN and VDDQ_BRN thresholds. The Early Warning

event signal is connected to the VIC1.7 interrupt channel. Software can manage the Early

Warning interrupt using the VIC1.7 channel bits in the VIC registers.

Note:

When the LVD is turned off, the VBAT feature is not supported.

The LVD logic consists of a lower power voltage band gap that provide an accurate voltage

reference. This voltage reference is used to create the voltage threshold levels that are

compared with the supply voltages.

When either voltage supply falls below the threshold for that supply, the LVD generates a

global reset.

1.2

Power down mode

In STR91xFA low power modes, the Flash automatically reduces its power consumption and

can be read immediately after wake-up.

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