AN2633 datasheet(11/48 Pages) STMICROELECTRONICS

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AN2633

Power supply and clocks

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1.3.8

Baud rate clock (BRCLK)

The baud rate clock is an internal clock derived from fMSTR that is used by the three on-chip

UART peripherals for baudrate generation. You can optionally divide the frequency by 2 by

setting the BR_SEL bit in the Clock control register (SCU_CLKCNTR). BRCLK can be gated

through the Peripheral Clock Gating Registers (see Section 1.3.13).

1.3.9

External memory interface (BCLK)

You can select the frequency of the EMI bus clock (BCLK) to be HCLK or HCLK/2 using the

EMIRATIO bit in the Clock control register (SCU_CLKCNTR). By default the frequency is

HCLK/2. The BCLK clock is available on the LFBGA package as an output pin. You can

disable the BCLK output by setting the BCLK_EN bit in the EMI register (SCU_GPIOEMI).

1.3.10

USB clock (USBCLK)

The USB clock can be derived from fMSTR when the frequency is 48 MHz or 96 MHz. If you

use another fMSTR frequency, the 48 MHz USBCLK must be sourced from the external pin

(GPIO pin). You select this using the USB_SEL [1:0] bits in the Clock control register

(SCU_CLKCNTR). USBCLK can be gated through the Peripheral Clock Gating Registers

(see Section 1.3.13).

1.3.11

Ethernet MAC clock

Special consideration regarding the Ethernet MAC: The external Ethernet PHY interface

device requires it’s own 25 MHz clock source. This clock can come from one of two sources:

●

A 25 MHz clock signal coming from a dedicated output pin (P5.2) of the STR91xFA. In

this case, the STR91xFA must use a 25 MHz signal on its main oscillator input in order

to pass this 25 MHz clock back out to the PHY device through pin P5.2. The advantage

here is that an inexpensive 25 MHz crystal may be used to source a clock to both the

STR91xFA and the external PHY device.

●

An external 25 MHz oscillator connected directly to the external PHY interface device.

In this case, the fOSC input clock doesn't have to be a 25 MHz crystal (from 4 MHz to

25 MHz).

You enable the output clock using the MAC_SEL bit in the Clock control register

(SCU_CLKCNTR).

1.3.12

External RTC calibration clock

The RTC_CLK can be enabled as an output on the JRTCK pin by setting the Calibration

Clock Output Enable bit in the RTC_CR register. The RTC_CLK is used for RTC oscillator

calibration. The RTC_CLK is active in Sleep mode and can be used as a system wake-up

control clock.

1.3.13

Peripheral clock gating

After reset, only the CPU, the Flash memory, the SRAM and a small subset of Peripheral

clock gating register 0 (SCU_PCGR0) and Peripheral clock gating register 1 (SCU_PCGR1)

registers) of the peripherals start operating. The other parts of the system remain stopped.

because the related PCGR bits are reset. To start them, you have to write 1 to the related

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