AN2555 - Application note

Modified features

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1.9

PLL and main on-chip oscillator

Compared to the ST10F269Zx, several modifications have been introduced:

●

PLL multiplication factors have been adapted in order to match the new frequency range.

●

On-chip main oscillator input frequency range has been reshaped, reducing it to a range from 4 to

12 MHz: this allows the power consumption to be reduced when the Real Time Clock is running in

Power Down mode and the on-chip main oscillator clock is used as the reference.

●

When the PLL is used, the CPU frequency range is 16 to 64 MHz.

Figure 1: ST10F276Z5 clock generation diagram gives a simplified description of the CPU clock

generation. Depending on the multiplication factor selected via Port 0 at reset, values are set for each

stage. The CPU clock is in fact generated mainly from a VCO (Voltage Controlled Oscillator) with the

following characteristics:

●

input range: 1 to 3.5 MHz, which is delivered from XTAL divided by a prescaler.

●

output range: 64 to 128 MHz that is then divided through Divider1 to generate the CPU clock

Figure 1.

ST10F276Z5 clock generation diagram

Table 8: ST10F269Zx vs. ST10F276Z5 PLL ratio lists the new PLL multiplication factors and the

corresponding frequency ranges for the ST10F276Z5.

All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the internal

oscillator amplifier, except for the Direct Drive mode (oscillator amplifier disabled, so no crystal or

resonator can be used). Vice versa, the clock can be forced through an external clock source only in

Direct Drive mode.

Table 8.

ST10F269Zx vs. ST10F276Z5 PLL ratio

P0.15-13

(P0H.7-5)

ST10F269Zx

ST10F276Z5

Notes

PLL factor

PLL factor

Input Frequency

Range (MHz)

111

4 to 8

Default configuration

110

5.3 to 10.6

101

4 to 8

100

6.4 to 12

011

1 to 64

Direct Drive

010

4 to 6.4

001

4 to 12

CPU clock via pre-scaler

000

4

Prescaler

VCO

Divider1

Divider2

Phase Comparator