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AN2555 bảng dữ liệu(PDF) 11 Page - STMicroelectronics |
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AN2555 bảng dữ liệu(HTML) 11 Page - STMicroelectronics |
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11 / 33 page ![]() AN2555 - Application note Modified features 11/33 duration of self-calibration depends on the CPU clock: It may take up to 40.629 ± 1 clock pulses. The user must poll this bit to know when self-calibration is complete in order to initialize the ADC module. This self-calibration is seen by the ST10F276Z5 as a conversion and thus bit ADCIR is set. The software must perform a dummy read of the ADDAT register and clear the ADCIR and ADCEIR flags before configuring the ADC module and starting the first conversion. New bit ADOFF, bit 6 of ADCON register ADCON (FFA0h / A0h) SFR Reset Value: 0000h The bit 6 of the ADCON register, reserved in previous ST10 devices, is now used to enable or disable the ADC. By default this bit is cleared and the ST10F276Z5 is compatible with the ST10F269Zx. Therefore there is no impact on the software, provided that the software does not write to this bit. Additional analog channels on Port1 A new multiplexer selects one out of up to 16+8 analog input channels (alternate functions of Port 5 and Port1). The selection of Port1 or Port5 as input of the ADC is made via ADCMUX, bit 0 of XMISC register. By default the multiplexer selects Port5, so there is no impact on the software as compared to an ST10F269Zx implementation. Note that XMISCEN, bit 10 of the XPERCON register, must be set to have access to the XMISC register. XMISC (EB46h) XREG Reset Value: --00h 15 14 13 12 11 10 9 8 7 6 543 210 ADCTC ADSTC ADCTC ADCIN ADWR ADBSY ADST ADOFF ADM ADCH RW RW RW RW RW R RW RW RW RW Bit Function Comment ADOFF ADC Disable ‘0’: Analog circuitry of A/D converter is on ‘1’: Analog circuitry of A/D converter is turned off (no consumption) New bit only for the ST10F276Z5. Reserved for the ST10F269Zx. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -- -- -- -- -- -- VREGOFF CANCK2 CANPAR ADCMUX RW RW RW RW Bit Function ADCMUX ‘0’ default configuration, analog inputs on port P5.y can be converted ‘1’ analog inputs on port P1.z can be converted, only 8 channel can be managed |
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