AN4149 datasheet(30/43 Pages) STMICROELECTRONICS

30 / 43 page

FOT PFC boost control loop

AN4149

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DocID023523 Rev 2

diode, 20 mA rated, will be activated in order to clamp the voltage. Please remember that

during normal operation the internal Zener will not have to clamp the voltage, because in

that case the power consumption of the device will increase considerably and its junction

temperature will also increase. The recommended operating condition for safe operation of

the device is below the minimum clamping voltage of the pin.

FOT PFC boost control loop

In order to find a compensation network ensuring stability over a large variety of operating

conditions and to prevent dangerous oscillations of the output voltage as a result of load

changes, it is necessary to have a correct understanding of the control loop of FOT PFC

systems.

The loop gain of PFC pre-regulators must have a very low crossover frequency (fc) so as to

keep VCOMP (error amplifier output) fairly constant over a given line cycle, filtering twice the

line frequency ripple on the output of the error amplifier, in order to ensure low THD (total

harmonic distortion). As a rule of thumb, fc should not exceed 20 Hz.

The small signal model of a PFC stage with a constant power load (the regulated DC-DC

converter) can be represented as a controlled current source delivering power to the output

capacitor.

Figure 15. Small signal model of a PFC stage with a constant-power load (DC-DC

converter)

The current generator:

is controlled by the small-signal AC control voltage:

and the system acts as a pure integrator and the resulting control-to-output transfer function

is:

Equation 85

AM13315v1

ˆi

ˆv

ˆvG

G( j )

ˆvj

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