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AN4149 bảng dữ liệu(PDF) 16 Page - STMicroelectronics

tên linh kiện AN4149
Giải thích chi tiết về linh kiện  Designing a CCM PFC pre-regulator based on the L4984D
PDF  43 Pages
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Designing a CCM FOT-controlled PFC
AN4149
16/43
DocID023523 Rev 2
Equation 41
Reading the ESR value of the datasheet of the output capacitor chosen, the power losses
associated to this ripple current can be easily calculated by:
Equation 42
If the PFC stage has to guarantee a specified hold-up time, the calculation of the output
capacitor is different. The value of the capacitor when the line voltage drops out, needed to
deliver the output power for a certain time (tHold) until the output voltage reaches the
required minimum voltage value (Voutmin), depends on the load and the value of the ripple.
When Voutmin is reached, a 'power fail' is detected, stopping the downstream system
supplied by the PFC. The worst case for the hold-up time is at minimum input voltage and
full load, with the line drop starting at the valley of the sine-varying ripple of the output
voltage.
Equation 43
Considering a 20% tolerance on the electrolytic capacitors, a value of 200
μF has been
chosen, using two capacitors of commercial value of 100
μF placed in parallel. The actual
hold-up time and ripple voltage with the selected value are:
Actual hold-up time:
Equation 44
Peak-to-peak output voltage ripple:
Equation 45
2.3.4
Boost inductor
As indicated in the specs in Section 2.1: Input specification, the maximum current ripple
factor Kr , that is the ratio of the maximum peak-to-peak current ripple amplitude to the
out
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