µPD30500, 30500A, 30500B

17

Data Sheet U12031EJ4V0DS00

Power Application Sequence

fixed. However, make sure that either of the power supplies does not remain turned on for 1 second or more while

the other remains off.

Parameter

Symbol

Condition

MIN.

MAX.

Unit

Power application delay

0

1

sec

Capacitance

Parameter

Symbol

Condition

MIN.

MAX.

Unit

Input capacitance

5pF

Output capacitance

7pF

Clock parameter

Parameter

Symbol

Condition

MIN.

MAX.

Unit

System clock high-level width

3.0

ns

System clock low-level width

3.0

ns

20

100

MHz

System clock cycle

10

50

ns

System clock jitter

System clock frequency > 66 MHz

±125

ps

System clock frequency

≤ 66 MHz

±250

ps

System clock rise time

2.0

ns

System clock fall time

2.0

ns

Mode clock cycle

256

ns

2. The operation is guaranteed if the internal operating frequency 100 MHz or higher.