UPD30500 datasheet(30/36 Pages) NEC

30 / 36 page

µPD30500, 30500A, 30500B

Data Sheet U12031EJ4V0DS00

APPENDIX DIFFERENCES BETWEEN THE VR5000 AND VR4310TM

Item

VR5000

VR4310

Operating frequency

Internal

200 MHz MAX.

167 MHz MAX.

External

100 MHz MAX.

83.3 MHz MAX.

Pipeline

2-way super scalar 5-stage

5-stage pipeline

pipeline

Cache

Primary instruction cache

32 Kbytes

16 Kbytes

Primary data cache

32 Kbytes

8 Kbytes

Secondary cache interface

Provided

None

Data protection

Byte parity

None

System bus

Write data transfer rate

9 types (DDDD/DDxDDx/

2 types (D/Dxx)

DDxxDDxx/DxDxDxDx/

DDxxxDDxxx/DDxxxxDDxxxx/

DxxDxxDxxDxx/

DDxxxxxxDDxxxxxx/DxxxDxxx)

Initialization pin at reset

ModeIn (dedicated serial pin)

DivMode (0:2)

Status after last data write

Access ends

Last data retained when transfer

rate is set

Integer operation unit

Corresponding instruction

MIPS I, II, III, IV instruction sets

MIPS I, II, III instruction sets

JTAG interface

None

Provided

SyncOut-SyncIn bus

None

Provided

Clock interface

Multiplication ratio of input

2, 3, 4, 5, 6, 7, 8

1.5, 2, 2.5, 3, 4, 5, 6

to internal

Division ratio of internal to

2, 3, 4, 5, 6, 7, 8

1.5, 2, 2.5, 3, 4, 5, 6

bus

Clock output

None

TClock

Power management mode

Standby mode (pipline does

Not provided

not operate)

PRId register

Imp = 0x23

Imp = 0x0B

UPD30500 bảng dữ liệu(PDF) 30 Page - NEC

UPD30500 bảng dữ liệu(HTML) 30 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

bảng dữ liệu tải về

Link URL