AN2870 datasheet(12/41 Pages) STMICROELECTRONICS

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Device blocks description

AN2870

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3.2.4

Zero current detection

The zero current detection (ZCD) block switches on the external PFC MOSFET as the

current through the boost inductor has gone to zero. This feature allows TM operation.

When the circuit is running, the signal for ZCD is obtained with an auxiliary winding coupled

with the boost inductor. A Schmidt trigger prevents false activations and an internal clamp

limits the voltage across the pin during normal operation in 0 V-5 V range. As at start-up no

signal is coming from the ZCD, an internal starter is needed in order to turn on the external

MOSFET and to arm the ZCD trigger.

The repetition rate of the starter is

≅ 6 kHz and this maximum frequency must be taken into

account at design time.

3.2.5

Driver

A totem pole buffer, with 300 mA source and 600 mA sink capability, allows driving an

external MOSFET. A pull-down circuit holds the output low when the device is in UVLO

conditions, to ensure that the external MOSFET cannot be turned on accidentally.

3.2.6

PFC protections

The device is provided with a double over-voltage protection (OVP).

The first over voltage protection, also called dynamic OVP, is activated immediately when

CTR pin (pin 7) goes above 3.4 V. The maximum voltage allowed for the output voltage

(VOVP) is defined by a resistive divider connected between output voltage and CTR pin.

In case of over voltage, the output of the E/A will tend to saturate low with a long constant

time, because of the bandwidth of this stage (typ. 10 Hz).

If the over-voltage lasts so long that the output of E/A goes below 2.25 V, the PF gate driver

is stopped and Tch timer is started. If E/A output voltage doesn’t return above 2.25 V after

the timer finishes its count, the IC is stopped in latch condition. This protection prevents

damages due to the connection to an excessive input voltage.

An intense high voltage (e.g. a surge) may break the upper resistors (one or more than one)

of the voltage dividers connected to input voltage (MULT biasing) or to output voltage (INV

and CTR biasing). Losing of the bias on pin INV implies losing of the control of the loop: in

fact E/A output saturates high and causes an increased output voltage, eventually not seen

by OVP because of failure on CTR voltage divider. The feedback disconnection protection

prevents this failure stopping the PF gate if INV voltage falls below 1.2 V and CTR pin goes

above 3.4 V. CTR pin can be also used to disable the IC pulling its voltage below 0.8 V.

Figure 6.

Protections block diagram

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