AN2839 datasheet(5/40 Pages) STMICROELECTRONICS

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AN2839

Designing an application with L6228

Doc ID 15104 Rev 1

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This spike is followed by a stable negative voltage due to the drop on RSENSE. One of the

two OUT pins of the bridge sees a similar behavior, but with a slightly larger voltage due to

the forward recovery time of the integrated freewheeling diode and the forward voltage drop

across it (see Figure 3). The typical duration of this spike is 30 ns. At the same time, the

other OUT pin of the same bridge sees a voltage above VS, due to the PCB inductance and

voltage drop across the high-side (integrated) freewheeling diode, as the current reverses

direction and flows into the bulk capacitor. It turns out that, in fast decay mode, the highest

differential voltage is observed between the two OUT pins of the same bridge, at the

beginning of the off time, and this must always be kept below 60 V(a). The same high-

voltage condition exists when a step is made and the direction of the current flow reverses in

the bridge.

Figure 3.

Currents and voltages during the dead time at the beginning of the off

time

Figure 4 on page 6 shows the voltage waveforms at the two OUT pins referring to a possible

practical situation, with a peak output current of 1.4 A, VS = 52 V, RSENSE = 0.33 Ω, TJ = 25

°C (approximately) and a good PCB layout. The below-ground spike amplitude is -2.65 V for

one output; the other OUT pin is at about 57 V. In these conditions, the total differential

voltage reaches almost 60 V, which is the absolute maximum rating for the DMOS. It is

extremely important to keep the differential voltage between two output pins belonging to the

same full bridge within rated values. This can be accomplished by correctly selecting the

value of the bulk capacitor and equivalent series resistance (ESR), according to the current

peaks and chopping style, and by adopting good layout practices to minimize PCB parasitic

inductances(a).

Refer to [3] in References.

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